Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. FIG. 1 is a simplified illustration of one type of PLD, the Field Programmable Gate Array (FPGA). An FPGA typically includes an array of configurable logic blocks (LBs 101a-101i) and programmable input/output blocks (I/Os 102a-102d). Some FPGAs also include additional logic blocks with special purposes (not shown), e.g., DLLS, RAM, and so forth. The LBs and I/O blocks are interconnected by a programmable interconnection array that includes a large number of interconnect lines 103 interconnected by programmable interconnect points (PIPs 104, shown as small circles in FIG. 1). A PIP can be, for example, a pass gate. When the pass gate is turned on, the two nodes on either side of the pass gate are electrically connected. When the pass gate is turned off, the two nodes are isolated from each other. Thus, by controlling the values on the gate terminals of the pass gates, circuit connections can easily be made and altered.
PIPs are often coupled into groups (e.g., group 105) that implement programmable routing multiplexer circuits. A programmable routing multiplexer circuit (a “routing multiplexer”) selects one of several interconnect lines (ILs) to provide a signal to a destination interconnect line or logic block.
The interconnection array and logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the interconnection array and logic blocks are configured. In Field Programmable Gate Arrays (FPGAs), for example, each configuration memory cell is implemented as a static memory cell. The values stored in these static memory cells are used, for example, to control the gate terminals of pass gates between pairs of interconnect lines. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
When subjected to unusual conditions such as cosmic rays or bombardment by neutrons or alpha particles, a static memory cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. Sometimes these “single event upsets” (SEUs) have no effect on the functionality of the chip, for example, when the static memory cell controls a pass gate between two unused interconnect lines. At other times, an SEU can change the functionality of a configured PLD such that the circuit no longer functions properly.
FIG. 2 shows an exemplary programmable routing multiplexer circuit in a PLD. This type of circuit is commonly included in FPGA interconnect structures, for example. The number of input signals varies and is often greater than eight, but eight input signals are shown in the exemplary circuits herein, for clarity. The circuit selects one of several different input signals and passes the selected signal to an output node. As will be explained, an SEU affecting one of the configuration memory cells in the circuit can short together two of the multiplexer input terminals.
The circuit of FIG. 2 includes eight input terminals IN0-IN7 and eight pass gates 200-207 that selectively pass one of signals IN0-IN7, respectively, to an internal node INT. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The signal on internal node INT is buffered by buffer BUF to provide output signal OUT. Buffer BUF, for example, can include two inverters 211, 212 coupled in series, and a pull-up (e.g., a P-channel transistor 113 to power high VDD) on internal node INT and driven by the node between the two inverters. However, buffer BUF can be implemented in many different ways.
Each pass gate 200-207 has a gate terminal driven by a memory cell M0-M7, respectively. Each memory cell Mn can include two cross-coupled inverters An and Bn, for example. However, memory cells M0-M7 can also be implemented in many different ways. For example, configuration memory cells in FPGAs typically include configuration logic for loading the configuration data. The details of memory cells M0-M7 are well known in the relevant arts and are omitted in the figures herein, for clarity.
The multiplexer circuit of FIG. 2 operates as shown in Table 1. At most, one of memory cells M0-M7 can be configured with a high value at any given time. Other configurations are not supported by the circuit. As shown in Table 1, the one memory cell with a high value selects the associated input signal IN0-IN7 to be passed to internal node INT, and hence to output node OUT. If none of memory cells MO-M7 is configured with a high value, output signal OUT is held at its initial high value by pull-up 213.
TABLE 1M7M6M5M4M3M2M1M0OUT00000000High00000001IN000000010IN100000100IN200001000IN300010000IN400100000IN501000000IN610000000IN7
In the multiplexer circuit of FIG. 2, the upset of any single memory cell (i.e., any SEU affecting any of memory cells M0-M7) causes a failure in the circuit. For example, assume that memory cell M0 stores a high value, while memory cells M1-M7 store low values. Pass gate 200 is enabled, and the selected input signal is IN0. Pass gates 201-207 are disabled. If the value in memory cell M0 is upset (i.e., changes to a low value), the path from input terminal IN0 to output terminal OUT is broken, and output signal OUT is no longer actively driven by node IN0. If the value in-memory cell M4 is upset (i.e., changes to a high value), pass gate 204 is enabled and there is a “short” (an inadvertent coupling) between input terminals IN0 and IN4. Similarly, if the value in memory cell M5 is upset, pass gate 205 is enabled and there is a short between nodes IN0 and IN5, and so forth. Thus, an SEU affecting one of the configuration memory cells in the circuit of FIG. 2 can short together two of the multiplexer input terminals.
Further, as operating voltages diminish, static memory cells become more susceptible to changes in state caused by SEUs. To reduce manufacturing costs, PLD manufacturers are aggressively reducing device sizes in their. PLDs. These smaller devices often operate at lower voltages. Therefore, all else being equal, there is a tendency towards greater SEU susceptibility in PLDs.
Circuits and methods have been developed to avoid the problems associated with SEUs. One well-known strategy for avoiding such problems is illustrated in FIG. 3. The illustrated circuit is called a triple modular redundancy (TMR) circuit. In essence, the required logic is implemented three times (i.e., in three modules), and the results generated by the three modules are compared. Any two module output signals that are the same are considered to be correct, and if the third module provides a different result the “dissenting vote” is thrown out.
The TMR circuit of FIG. 3 includes modules M1-M3, representing three implementations of the same logical function. Each module has a respective output signal 01-03 that drives voting circuit VC. Voting circuit VC implements the function (01 AND 02) OR (02 AND 03) OR (01 AND 03) and provides the result as the output signal of the circuit.
Clearly, this approach overcomes any SEU that affects the functionality of only one of the three modules M1-M3. The module affected by the event produces an incorrect result, which is overridden in the voting circuit by the other two modules. However, while the circuit of FIG. 3 works well for errors that occur within one of modules M1-M3, it does not work when two of the three modules are in error, causing two of the three inputs to the voting circuit to be incorrect. Such a situation can occur, for example, when an SEU causes a short between two input terminals of a routing multiplexer, and the two input terminals are coupled to nodes in two different modules.
Circuits implemented in a PLD are not necessarily implemented in discrete regions of the device. The best implementation of the circuit of FIG. 3 in terms of performance or minimizing resource usage might be to physically intermix the logic for the three modules M1-M3. In that case, internal nodes in two different modules can easily be separated by only a single disabled PIP in one routing multiplexer.
Similarly, SEUs can cause inadvertent connections between a node in one of the modules M1-M3 and a node in the voting circuit VC, or between two different nodes in voting circuit VC, or between nodes in two different voting circuits.
Therefore, it is desirable to facilitate the use of TMR in programmable systems and devices by providing programmable routing multiplexer circuits in which the input terminals cannot be shorted together by a single SEU.